4. ADC architecture selection and channel budget impact

Once the channel count, per-channel bandwidth, and accuracy targets are fixed, the next decision that reshapes the entire channel budget is the ADC topology. Three families dominate data acquisition design: multiplexed (a single ADC front-ended by an analog mux), simultaneous-sampling (one sample-and-hold per channel feeding a shared or parallel converter core), and per-channel (a dedicated ADC for every input). Each choice changes cost, achievable aggregate throughput, channel density, and — critically — the timing and accuracy terms that must appear in the budget. Selecting the topology is therefore not a component-picking exercise but a budget-allocation decision.

How each topology spends the budget

A multiplexed architecture amortizes one converter across N inputs. The mux adds on-resistance and charge injection, and the shared sample-and-hold must settle to the required accuracy within the allotted per-channel slot. The dominant budget term becomes settling time: the source impedance, mux R_on, and the ADC sampling capacitor form an RC network whose settling must complete to better than ½ LSB before the conversion aperture. Aggregate throughput is the converter rate divided by N (plus overhead), so channel density is high but per-channel rate is low. Cost per channel is the lowest of the three, which is why multiplexed front-ends dominate slow, high-count monitoring.

A simultaneous-sampling architecture gives every channel its own track-and-hold but may share converter cores. This preserves relative phase between channels — essential for power quality, motor current/voltage pairs, and phased arrays — while still amortizing silicon. The budget now carries a channel-to-channel skew term (the aperture mismatch between holds) and a crosstalk term from adjacent holds, but the per-channel settling requirement relaxes because each hold has a full conversion interval to acquire. Throughput scales with the number of parallel cores, not with N.

A per-channel architecture removes the mux and the shared hold entirely. Each channel owns its converter, so there is no settling contention, no skew between channels beyond clock distribution, and no crosstalk through a shared front-end. The price is silicon area and power: cost scales linearly with N, and channel density is limited by package and PCB real estate. This is the choice when every channel must run at full rate with independent gain/offset and when isolation or sensor-specific front-ends are required.

Topology comparison at a glance

Worked example: sizing a 16-channel budget

Consider a 16-channel acquisition task with 16-bit resolution, a 10 kSPS per-channel target, and a source impedance of 1 kΩ. A multiplexed 16-bit SAR at 500 kSPS gives an aggregate slot budget of 500 kSPS ÷ 16 ≈ 31.25 kSPS per channel — comfortably above 10 kSPS, leaving margin for settling. The settling check: with a 1 kΩ source, a 100 Ω mux R_on, and a 20 pF sampling capacitor, τ ≈ 22 ns; to settle 16 bits (≈ 11τ) requires ≈ 240 ns, well inside the 32 µs slot. The multiplexed choice passes the budget with large margin and is the lowest-cost option.

Now raise the per-channel rate to 200 kSPS. The multiplexed slot shrinks to 500 kSPS ÷ 16 ≈ 31.25 kSPS — below target, so multiplexing fails on throughput alone. A simultaneous-sampling front-end with four parallel 16-bit cores at 800 kSPS each serves four channels per core, giving 200 kSPS per channel with aperture-matched holds; the budget now carries a skew term (typically a few hundred picoseconds) that must be checked against the phase-error requirement. If the application also demands independent per-channel gain and full-rate isolation, per-channel converters become the only correct answer, and the budget shifts from settling and skew to power and board area.

Translating topology into budget line items

The topology decision must be written into the channel budget as explicit terms, not left implicit. For a multiplexed design, add a settling allocation per slot and verify it against the worst-case source impedance; also add a mux charge-injection error term that appears as an offset step when switching between channels with different source impedances. For simultaneous sampling, add a skew allocation derived from the aperture mismatch specification and the signal's maximum slew rate — the phase error is skew × 2πf × amplitude, so a 1 ns skew at 10 kHz on a full-scale sine is already a measurable fraction of an LSB at 16 bits. For per-channel designs, the budget shifts toward reference and clock distribution: a shared reference must hold its accuracy across all converters, and clock skew between converters becomes the new phase term.

A practical selection procedure is to compute, for each candidate topology, the binding constraint: the term that consumes the largest fraction of its allocated error or time budget. If settling consumes more than about 60% of the multiplexed slot, the design has no margin for source-impedance variation and should either buffer the inputs or move to simultaneous sampling. If skew consumes more than half the phase-error allowance, per-channel conversion or a tighter aperture-matched front-end is required. The topology that leaves the most balanced margin across settling, skew, and crosstalk is the one that will survive production tolerances.

Channel density and physical constraints

Channel density is not only a silicon question. A multiplexed 64-channel front-end may fit in a single small package, but the mux input capacitance and the trace routing to 64 sources create parasitic coupling that must be budgeted as crosstalk. Simultaneous-sampling parts with many holds increase pin count and package size, and the per-channel hold capacitors demand careful layout to avoid injection from adjacent channels. Per-channel converters multiply the reference decoupling and clock fan-out, so the density limit is often set by the PCB, not the die. When the channel count is high and the per-channel rate is low, multiplexing wins on density; when the count is moderate and phase coherence matters, simultaneous sampling wins on signal integrity; when the count is low and every channel is independent, per-channel wins on simplicity of the budget.

The final selection should be recorded alongside the budget as a short decision note: the chosen topology, the binding constraint, the margin left on settling, skew, and crosstalk, and the conditions under which the decision would be revisited (for example, if per-channel rate rises above the multiplexed slot limit or if source impedance exceeds the settling assumption). This note becomes the traceable link between the architecture choice and every downstream budget line, and it is what allows the sampling plan to be revised without re-deriving the entire channel budget from scratch.