3. Data acquisition and sensor integration

Yield analysis rarely fails because the statistics are too weak. It fails because the data feeding those statistics is fragmented, misaligned in time, or missing the context that explains why a wafer or lot was processed the way it was. A single yield excursion on a 300 mm line can involve a chamber pressure drift recorded by SCADA, a recipe step change logged in MES, an endpoint trace captured by FDC, and a film-thickness measurement from metrology. If these four sources are not integrated into a common timeline with shared identifiers, the engineer sees four unrelated symptoms instead of one causal chain.

This section explains what each source contributes, how they differ in sampling behavior and semantics, and how to integrate them into a yield-analysis-ready dataset.

The Four Data Domains and What They Actually Contain

SCADA (Supervisory Control and Data Acquisition) sits closest to the equipment and facility layer. It polls PLCs and sensors at fixed intervals — commonly 1 s to 10 s — and records equipment states, valve positions, pump speeds, chamber pressures, coolant temperatures, and alarm bits. SCADA data is high-frequency and continuous, but it is usually equipment-centric: it knows that chamber B was at 2.3 Torr at 14:32:07, not which lot was inside.

MES (Manufacturing Execution System) is the transactional backbone. It records lot and wafer identity, routing, recipe assignment, operator actions, hold/release events, and equipment state transitions such as RUN, IDLE, DOWN. MES is event-driven and low-frequency, but it provides the context that binds every other source to a physical product unit. Without MES, SCADA and FDC traces cannot be attributed to a lot.

FDC (Fault Detection and Classification) captures per-run process traces — RF power, gas flows, throttle valve angle, endpoint signals — at high frequency (often 1–10 Hz) and computes summary statistics and fault flags per step. FDC is the bridge between raw sensor behavior and process outcome: it tells you that step 3 of recipe ETCH_A17 ran 4.2 s longer than the historical mean.

Metrology provides the physical result: film thickness, critical dimension (CD), overlay, defect counts, and electrical test parameters. Metrology is sparse — often one measurement per lot or per few wafers — and is the closest proxy to yield itself.

Integration Architecture: From Sensor to Yield Table

The practical goal is a single analysis table where each row is a wafer (or lot) and columns include MES context, FDC summary statistics, SCADA-derived equipment health features, and metrology results. The diagram below shows how these domains converge.

Data Flow: Sensor Layer to Yield Analysis Table SCADA PLC / sensor polling 1–10 s interval pressure, temp, valve MES Lot / wafer tracking Event-driven recipe, route, hold FDC Per-run trace capture 1–10 Hz RF, gas, endpoint Metrology thickness, CD, defect Integration Layer Timestamp alignment Entity resolution (lot ↔ chamber ↔ run) Feature extraction Unit normalization Missing-data policy Data quality flags join key: lot_id + wafer_id + process_step + timestamp Yield Analysis Table Column Source lot_id, wafer_id MES recipe_id, step_no MES chamber_pressure_mean SCADA rf_power_std, step_duration FDC film_thickness_nm Metrology defect_count Metrology yield_flag (pass/fail) E-test one row per wafer per process step Join key: lot_id + wafer_id + process_step + timestamp

Timestamp Alignment and Entity Resolution

The hardest integration problem is not connectivity — it is alignment. SCADA timestamps come from the PLC clock, FDC timestamps from the equipment host, MES timestamps from the server, and metrology timestamps from the metrology tool. Clock skew of even a few seconds can shift a SCADA pressure reading into the wrong process step.

A practical alignment procedure:

  1. Normalize all timestamps to UTC and record the original timezone offset as a separate column. Never discard it.
  2. Establish a step boundary table from MES or FDC step-change events. Each row defines lot_id, wafer_id, process_step, step_start_utc, step_end_utc.
  3. Assign SCADA and FDC samples to steps using interval overlap. A sample at time t belongs to the step where step_start_utc ≤ t < step_end_utc.
  4. Resolve entity ambiguity: if two lots overlap on the same chamber, use MES chamber-assignment records to disambiguate. If unavailable, flag the interval as ambiguous_assignment rather than guessing.
Common pitfall: Using the SCADA timestamp as the primary key without checking clock drift. A 30-second drift on a 45-second etch step will misattribute an entire step's data. Always validate by comparing step duration computed from SCADA transitions against MES step duration; a consistent offset indicates clock skew, not process variation.

Feature Extraction: Turning Traces into Yield Predictors

Raw traces are too granular for yield modeling. The integration layer must reduce them to features that carry process meaning. For a plasma etch step, typical FDC-derived features include:

Feature Source Computation Yield relevance
rf_power_mean FDC Mean over step window Etch rate stability
rf_power_std FDC Standard deviation over step Plasma instability indicator
pressure_drift SCADA End-of-step minus start-of-step Chamber condition / leak
step_duration_dev FDC Actual minus recipe target Endpoint detection reliability
throttle_angle_mean SCADA Mean valve position Pump/valve degradation

Each feature should be stored with a data_quality_flag: OK, MISSING, CLIPPED, or AMBIGUOUS. Downstream yield models must be able to exclude or impute flagged rows explicitly, not silently.

Metrology Integration and Sparse-Data Handling

Metrology is the ground truth for many yield models, but it is sparse. A common pattern is one measurement per lot at a specific step. When joining metrology to the wafer-level table, two decisions matter:

  • Measurement-to-wafer mapping: if metrology measures a representative wafer, propagate the value to the lot with a measurement_scope = lot flag. Do not pretend it is wafer-specific.
  • Time-lag handling: metrology often occurs hours after the process step. Join on lot_id and process_step, not on timestamp proximity.
Practical rule: Build the yield table at the finest grain your join keys support. If metrology is lot-level, keep the table at lot-level for metrology columns and wafer-level for FDC/SCADA columns, using a grain column to make the distinction explicit. This prevents accidental duplication during aggregation.

Data Quality Checks Before Yield Analysis

Before feeding the integrated table into a yield model, run these checks:

  1. Row count reconciliation: expected wafers per lot × number of lots should match the table row count within the known metrology sampling rate.
  2. Null rate by column: any column with >20% nulls should be investigated — it usually indicates a broken integration path, not random missingness.
  3. Timestamp monotonicity: within a lot, step start times must be strictly increasing. Violations indicate clock or routing errors.
  4. Unit consistency: pressure in Torr vs. Pa, power in W vs. kW. Store units in column metadata and validate ranges against recipe limits.
  5. Outlier sanity: a rf_power_mean of 0 or 5000 W on a 500 W recipe is a sensor or scaling fault, not a process excursion.

When these checks pass, the integrated dataset becomes a reliable foundation for correlation analysis, fault signature extraction, and yield prediction. The next step — using this data to identify yield-limiting process signatures — depends entirely on the integrity established here.

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